MC9S12XD256MAL Datasheet, PDF (229/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

BFINS
Bit Field Insert
Chapter 6 XGATE (S12XGATEV2)
BFINS
Operation
RS1[w:0] ⇒ RD[(w+o):o];
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD starting at
position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0
as a RS1, this command can be used to clear bits.
15
7
43
0
W4
O4
RS2
15
3
0
RS1
Bit Field Insert
15
5
2
0
W4=3, O4=2
RD
CCR Effects
NZVC
∆ ∆ 0—
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: 0; cleared.
C: Not affected.
Code and CPU Cycles
Source Form
BFINS RD, RS1, RS2
Address
Mode
TRI
01101
Machine Code
RD
RS1
Cycles
RS2 1 1
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
229