MC9S12XD256MAL Datasheet, PDF (1025/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

24.0.5.63 Port AD1 Reduced Drive Register 1 (RDR1AD1)
7
R
RDR1AD17
W
6
RDR1AD16
5
RDR1AD15
4
RDR1AD14
3
RDR1AD13
2
RDR1AD12
1
RDR1AD11
0
RDR1AD10
Reset
0
0
0
0
0
0
0
0
Figure 24-65. Port AD1 Reduced Drive Register 1 (RDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[7:0] output pin as either full or reduced. If
the port is used as input this bit is ignored.
Table 24-57. RDR1AD1 Field Descriptions
Field
Description
7–0
RDR1AD1[7:0]
Reduced Drive Port AD1 Register 1
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
24.0.5.64 Port AD1 Pull Up Enable Register 0 (PER0AD1)
7
6
5
4
3
2
1
R
PER0AD115 PER0AD114 PER0AD113 PER0AD112 PER0AD111 PER0AD110 PER0AD19
W
0
PER0AD18
Reset
0
0
0
0
0
0
0
0
Figure 24-66. Port AD1 Pull Up Enable Register 0 (PER0AD1)
Read: Anytime.
Write: Anytime.
This register activates a pull-up device on the respective PAD[15:8] pin if the port is used as input.
This bit has no effect if the port is used as output. Out of reset no pull-up device is enabled.
Table 24-58. PER0AD1 Field Descriptions
Field
7–0
Pull Device Enable Port AD1 Register 0
PER0AD1[15:8] 0 Pull-up device is disabled.
1 Pull-up device is enabled.
Description