MC9S12XD256MAL Datasheet, PDF (750/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.2 Debug Status Register (DBGSR)
Address: 0x0021
7
R TBF
W
Reset
—
POR
0
6
5
4
3
2
EXTF
0
0
0
SSF2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-4. Debug Status Register (DBGSR)
1
SSF1
0
0
0
SSF0
0
0
Read: Anytime
Write: Never
Table 20-6. DBGSR Field Descriptions
Field
7
TBF
6
EXTF
2–0
SSF[2:0]
Description
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was
met since arming. This bit is cleared when ARM in DBGC1 is written to a one.
0 External tag hit has not occurred
1 External tag hit has occurred
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 20-7.
Table 20-7. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0]
000
001
010
011
100
101,110,111
Current State
State0 (disarmed)
State1
State2
State3
Final State
Reserved
MC9S12XDP512 Data Sheet, Rev. 2.21
752
Freescale Semiconductor