MC9S12XD256MAL Datasheet, PDF (438/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are
read-only
Table 10-16. CANIDAC Register Field Descriptions
Field
Description
5:4
Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization
IDAM[1:0] (see Section 10.4.3, “Identifier Acceptance Filter”). Table 10-17 summarizes the different settings. In filter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
2:0
Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see
IDHIT[2:0] Section 10.4.3, “Identifier Acceptance Filter”). Table 10-18 summarizes the different settings.
IDAM1
0
0
1
1
Table 10-17. Identifier Acceptance Mode Settings
IDAM0
0
1
0
1
Identifier Acceptance Mode
Two 32-bit acceptance filters
Four 16-bit acceptance filters
Eight 8-bit acceptance filters
Filter closed
Table 10-18. Identifier Acceptance Hit Indication
IDHIT2
IDHIT1
IDHIT0
Identifier Acceptance Hit
0
0
0
Filter 0 hit
0
0
1
0
1
0
0
1
1
Filter 1 hit
Filter 2 hit
Filter 3 hit
1
0
0
1
0
1
1
1
0
Filter 4 hit
Filter 5 hit
Filter 6 hit
1
1
1
Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
10.3.2.13 MSCAN Reserved Register
This register is reserved for factory testing of the MSCAN module and is not available in normal system
operation modes.
MC9S12XDP512 Data Sheet, Rev. 2.21
438
Freescale Semiconductor