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MC9S12XD256MAL Datasheet, PDF (326/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.10 Timer Interrupt Enable Register (TIE)
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 7-15. Timer Interrupt Enable Register (TIE)
Read or write: Anytime
All bits reset to zero.
The bits C7IâC0I correspond bit-for-bit with the ï¬ags in the TFLG1 status register.
Table 7-13. TIE Field Descriptions
Field
7:0
C[7:0]I
Description
Input Capture/Output Compare âxâ Interrupt Enable
0 The corresponding ï¬ag is disabled from causing a hardware interrupt.
1 The corresponding ï¬ag is enabled to cause an interrupt.
MC9S12XDP512 Data Sheet, Rev. 2.21
326
Freescale Semiconductor
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