MC9S12XD256MAL Datasheet, PDF (227/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

BFEXT
Bit Field Extract
Chapter 6 XGATE (S12XGATEV2)
BFEXT
Operation
RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)]
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD.
The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
15
7
43
0
W4
O4
RS2
15
5
2
0
W4=3, O4=2
RS1
Bit Field Extract
15
0
3
0
RD
CCR Effects
NZVC
0∆0∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: 0; cleared.
C: Not affected.
Code and CPU Cycles
Source Form
BFEXT RD, RS1, RS2
Address
Mode
TRI
01100
Machine Code
RD
RS1
Cycles
RS2 1 1
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
227