MC9S12XD256MAL Datasheet, PDF (83/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.1 Module Memory Map
Table 2-1 gives an overview on all CRG registers.
Table 2-1. CRG Memory Map
Address
Offset
Use
0x_00
CRG Synthesizer Register (SYNR)
0x_01
0x_02
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)¹
0x_03
CRG Flags Register (CRGFLG)
0x_04
CRG Interrupt Enable Register (CRGINT)
0x_05
CRG Clock Select Register (CLKSEL)
0x_06
CRG PLL Control Register (PLLCTL)
0x_07
CRG RTI Control Register (RTICTL)
0x_08
0x_09
0x_0A
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)²
CRG Test Control Register (CTCTL)³
0x_0B
CRG COP Arm/Timer Reset (ARMCOP)
1 _{CTFLG is intended for factory test purposes only.}
2 _{FORBYP is intended for factory test purposes only.}
3 _{CTCTL is intended for factory test purposes only.}
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
83