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MC9S12XD256MAL Datasheet, PDF (518/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 12 Serial Peripheral Interface (S12SPIV4)
12.2.3 SS â Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is conï¬gured as a master and it is used as an input to receive the slave select
signal when the SPI is conï¬gured as slave.
12.2.4 SCK â Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3 Memory Map and Register Deï¬nition
This section provides a detailed description of address space and registers used by the SPI.
12.3.1 Module Memory Map
The memory map for the SPI is given in Figure 12-2. The address listed for each register is the sum of a
base address and an address offset. The base address is deï¬ned at the SoC level and the address offset is
deï¬ned at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
SPICR1
R
SPIE
W
SPICR2 R
0
W
SPIBR
R
0
W
SPISR
R SPIF
W
Reserved R
W
SPIDR
R
Bit 7
W
Reserved R
W
Reserved R
W
6
SPE
0
SPPR2
0
5
4
3
SPTIE
MSTR
CPOL
0
MODFEN BIDIROE
0
SPPR1
SPPR0
SPTEF
MODF
0
6
5
4
3
= Unimplemented or Reserved
Figure 12-2. SPI Register Summary
2
CPHA
0
SPR2
0
2
1
SSOE
SPISWAI
SPR1
0
1
Bit 0
LSBFE
SPC0
SPR0
0
Bit 0
MC9S12XDP512 Data Sheet, Rev. 2.21
518
Freescale Semiconductor
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