MC9S12XD256MAL Datasheet, PDF (324/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
7
R
OM7
W
6
OL7
5
OM6
4
OL6
3
OM5
2
OL5
1
OM4
0
OL4
Reset
0
0
0
0
0
0
0
0
Figure 7-11. Timer Control Register 1 (TCTL1)
7
R
OM3
W
6
OL3
5
OM2
4
OL2
3
OM1
2
OL1
1
OM0
0
OL0
Reset
0
0
0
0
0
0
0
0
Figure 7-12. Timer Control Register 2 (TCTL2)
Read or write: Anytime
All bits reset to zero.
Table 7-9. TCTL1/TCTL2 Field Descriptions
Field
OM[7:0]
7, 5, 3, 1
OL[7:0]
6, 4, 2, 0
Description
OMx — Output Mode
OLx — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful
OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.
See Table 7-10.
Table 7-10. Compare Result Output Action
OMx
0
0
1
1
OLx
Action
0
Timer disconnected from output pin logic
1
Toggle OCx output line
0
Clear OCx output line to zero
1
Set OCx output line to one
NOTE
To enable output action by OMx and OLx bits on timer port, the
corresponding bit in OC7M should be cleared.
MC9S12XDP512 Data Sheet, Rev. 2.21
324
Freescale Semiconductor