MC9S12XD256MAL Datasheet, PDF (1030/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).
NOTE
Port K is not available in 80-pin packages.
24.0.7.5 Port T
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose
I/O, or with the channels of the enhanced capture timer.
24.0.7.6 Port S
This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for general-
purpose I/O, or with the SCI and SPI subsystems.
The SPI0 pins can be re-routed. Refer to Section 24.0.5.33, “Module Routing Register (MODRR)”.
NOTE
PS[7:4] are not available in 80-pin packages.
24.0.7.7 Port M
This port is associated with the CAN4 and 0 and SPI0. Port M pins PM[7:0] can be used for either general
purpose I/O, or with the CAN, SCI and SPI subsystems.
The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to Section 24.0.5.33, “Module Routing Register
(MODRR)”.
NOTE
PM[7:6] are not available in 80-pin packages.
24.0.7.8 Port P
This port is associated with the PWM, SPI1. Port P pins PP[7:0] can be used for either general purpose I/
O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1. If the PWM is enabled the pins become
PWM output channels with the exception of pin 7 which can be PWM input or output. If SPI1is enabled
and PWM is disabled, the respective pin configuration is determined by status bits in the SPI.
The SPI1 pins can be re-routed. Refer to Section 24.0.5.33, “Module Routing Register (MODRR)”.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion (Section 24.0.8, “Pin
Interrupts”).
NOTE
PP[6] is not available in 80-pin packages.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor