MC9S12XD256MAL Datasheet, PDF (258/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
LDB
Load Byte from Memory
(Low Byte)
LDB
Operation
M[RB, #OFFS5 ⇒ RD.L; $00 ⇒ RD.H
M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H
M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI;¹
RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H
Loads a byte from memory into the low byte of register RD. The high byte is cleared.
CCR Effects
NZVC
————
N: Not affected.
Z: Not affected.
V: Not affected.
C: Not affected.
Code and CPU Cycles
Source Form
LDB RD, (RB, #OFFS5)
LDB RD, (RS, RI)
LDB RD, (RS, RI+)
LDB RD, (RS, -RI)
Address
Mode
IDO5
IDR
IDR+
-IDR
01000
01100
01100
01100
Machine Code
RD
RB
RD
RB
RD
RB
RD
RB
Cycles
OFFS5
Pr
RI
00
Pr
RI
01
Pr
RI
10
Pr
1.If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not
be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H
MC9S12XDP512 Data Sheet, Rev. 2.21
258
Freescale Semiconductor