MC9S12XD256MAL Datasheet, PDF (1326/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix G Detailed Register Map
0x0138–0x013F Asynchronous Serial Interface (SCI5) Map (continued)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R
0
0x013D SCI5SR2
AMAP
W
0
TXPOL RXPOL
R R8
0
0
0
0x013E SCI5DRH
T8
W
R R7
R6
R5
R4
R3
0x013F SCI5DRL
W T7
T6
T5
T4
T3
1 _{Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to zero}
2 _{Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to one}
Bit 2
BRK13
0
R2
T2
Bit 1
TXDIR
0
R1
T1
Bit 0
RAF
0
R0
T0
0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map
Address Name
Bit 7
0x0140
0x0141
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
0x0148
0x0149
0x014A
0x014B
0x014C
0x014D
0x014E
0x014F
R
CAN0CTL0
RXFRM
W
R
CAN0CTL1
CANE
W
R
CAN0BTR0
SJW1
W
R
CAN0BTR1
SAMP
W
R
CAN0RFLG
WUPIF
W
R
CAN0RIER
WUPIE
W
R
0
CAN0TFLG
W
R
0
CAN0TIER
W
R
0
CAN0TARQ
W
R
0
CAN0TAAK
W
R
0
CAN0TBSEL
W
R
0
CAN0IDAC
W
R
0
Reserved
W
R
0
CAN0MISC
W
R RXERR7
CAN0RXERR
W
R TXERR7
CAN0TXERR
W
Bit 6
RXACT
CLKSRC
SJW0
TSEG22
CSCIF
CSCIE
0
0
0
0
0
0
0
0
RXERR6
TXERR6
Bit 5
CSWAI
LOOPB
BRP5
TSEG21
RSTAT1
RSTATE1
0
0
0
0
0
IDAM1
0
0
RXERR5
TXERR5
Bit 4
SYNCH
LISTEN
BRP4
TSEG20
RSTAT0
RSTATE0
0
0
0
0
0
IDAM0
0
0
RXERR4
TXERR4
Bit 3
TIME
BORM
BRP3
TSEG13
TSTAT1
TSTATE1
0
0
0
0
0
0
0
0
RXERR3
TXERR3
Bit 2
WUPE
WUPM
BRP2
TSEG12
TSTAT0
TSTATE0
TXE2
TXEIE2
ABTRQ2
ABTAK2
TX2
IDHIT2
0
0
RXERR2
TXERR2
Bit 1
SLPRQ
SLPAK
BRP1
TSEG11
OVRIF
OVRIE
TXE1
TXEIE1
ABTRQ1
ABTAK1
TX1
IDHIT1
0
0
RXERR1
TXERR1
Bit 0
INITRQ
INITAK
BRP0
TSEG10
RXF
RXFIE
TXE0
TXEIE0
ABTRQ0
ABTAK0
TX0
IDHIT0
0
BOHOLD
RXERR0
TXERR0
1328
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor