MC9S12XD256MAL Datasheet, PDF (976/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
External Signal Description
This section lists and describes the signals that do connect off-chip.
24.0.3 Signal Properties
Table 24-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section ,
“Functional Description” for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 24-1. Pin Functions and Priorities (Sheet 1 of 5)
Port
—
A
B
E
K
T
Pin Name
BKGD
PA[7:0]
PB[7:0]
PE[7]
PE[6:5]
Pin Function
and Priority
MODC¹
BKGD
GPIO
GPIO
XCLKS¹
ECLKX2
GPIO
GPIO
PE[4]
PE[3:2]
PE[1]
PE[0]
PK[7]
PK[5:0]
PT[7:0]
ECLK
GPIO
GPIO
IRQ
GPIO
XIRQ
GPIO
GPIO
GPIO
IOC[7:0]
GPIO
I/O
Description
I MODC input during RESET
I/O S12X_BDM communication pin
I/O General-purpose I/O
I/O General-purpose I/O
I External clock selection input during RESET
I Free-running clock output at Core Clock rate (ECLK x 2)
I/O General-purpose I/O
I/O General-purpose I/O
O
Free-running clock output at the Bus Clock rate or
programmable divided in normal modes
I/O General-purpose I/O
I/O General-purpose I/O
I Maskable level- or falling edge-sensitive interrupt input
I/O General-purpose I/O
I Non-maskable level-sensitive interrupt input
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O Enhanced Capture Timer Channels 7–0 input/output
I/O General-purpose I/O
Pin Function
after Reset
BKGD
GPIO
GPIO
GPIO
GPIO
MC9S12XDP512 Data Sheet, Rev. 2.21
978
Freescale Semiconductor