MC9S12XD256MAL Datasheet, PDF (695/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
19.3 Memory Map and Register Definition
A summary of the registers associated with the DBG sub-block is shown in Figure 19-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
19.3.1 Register Descriptions
This section consists of the DBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG and COMRV[1:0]
Address
0x0020
Register
Name
DBGC1
Bit 7
R
ARM
W
6
0
TRIG
5
XGSBPE
4
BDM
3
2
DBGBRK
1
Bit 0
COMRV
0x0021 DBGSR R TBF
EXTF
0
0
0
SSF2
SSF1
SSF0
W
0x0022 DBGTCR R
W
TSOURCE
TRANGE
TRCMOD
TALIGN
0x0023
DBGC2
R
0
0
0
0
W
CDCM
ABCM
0x0024 DBGTBH R Bit 15
14
13
12
11
10
W
9
Bit 8
0x0025 DBGTBL R Bit 7
6
5
4
3
2
1
Bit 0
W
0x0026 DBGCNT R
0
W
CNT
0x0027 DBGSCRX R
0
0
0
0
SC3
SC2
W
0x0028 DBGXCTL¹ R
0
(COMPA/C) _W
NDB
TAG
BRK
RW
RWE
0x0028 DBGXCTL² R
(COMPB/D) _W ^SZE
SZ
TAG
BRK
RW
RWE
1. This represents the contents if the comparator A or C control register is blended into this address
2. This represents the contents if the comparator B or D control register is blended into this address
SC1
SC0
SRC COMPE
SRC COMPE
= Unimplemented or Reserved
Figure 19-2. DBG Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
697