MC9S12XD256MAL Datasheet, PDF (1012/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-36. RDRP Field Descriptions
Field
Description
7–0
Reduced Drive Port P
RDRP[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
24.0.5.38 Port P Pull Device Enable Register (PERP)
7
R
PERP7
W
6
PERP6
5
PERP5
4
PERP4
3
PERP3
2
PERP2
1
PERP1
0
PERP0
Reset
0
0
0
0
0
0
0
0
Figure 24-40. Port P Pull Device Enable Register (PERP)
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input.
This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
Table 24-37. PERP Field Descriptions
Field
Description
7–0
Pull Device Enable Port P
PERP[7:0] 0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
24.0.5.39 Port P Polarity Select Register (PPSP)
R
W
Reset
7
PPSP7
0
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
0
0
0
0
0
Figure 24-41. Port P Polarity Select Register (PPSP)
1
PPSP1
0
0
PPSP0
0
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor