MC9S12XD256MAL Datasheet, PDF (413/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
9.5 Resets
The reset state of each individual bit is listed in Section 9.3, “Memory Map and Register Definition,” which
details the registers and their bit-fields.
9.6 Interrupts
IICV2 uses only one interrupt vector.
Table 9-8. Interrupt Summary
Interrupt Offset
IIC
—
Interrupt
Vector
—
Priority
Source
Description
— IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set
bits in IBSR may cause an interrupt based on arbitration
register
lost, transfer complete or address detect
conditions
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
1. Arbitration lost condition (IBAL bit set)
2. Byte transfer condition (TCF bit set)
3. Address detect condition (IAAS bit set)
The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to
the IBF bit in the interrupt service routine.
9.7 Initialization/Application Information
9.7.1 IIC Programming Examples
9.7.1.1 Initialization Sequence
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
frequency from system clock.
2. Update the IIC bus address register (IBAD) to define its slave address.
3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.
4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive
mode and interrupt enable or not.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
413