MC9S12XD256MAL Datasheet, PDF (446/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
1 _{Not applicable for receive buffers}
2 _{Read-only for CPU}
3 _{Read-only for CPU}
Figure 10-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 10-25.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation¹.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit priority registers are 0 out of reset.
MC9S12XDP512 Data Sheet, Rev. 2.21
446
Freescale Semiconductor