MC9S12XD256MAL Datasheet, PDF (81/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

2.1.3 Block Diagram
Figure 2-1 shows a block diagram of the CRG.
Chapter 2 Clocks and Reset Generator (S12CRGV6)
S12X_MMC ^{Illegal Address Reset}
Voltage ^{Power on Reset}
Regulator Low Voltage Reset
RESET
CRG
XCLKS
Clock
Monitor
EXTAL Oscillator
CM fail
OSCCLK
XTAL
Reset
Generator
Clock Quality
Checker
COP RTI
XFC
V_DDPLL
V_SSPLL
PLLCLK
PLL
Registers
Clock and Reset
Control
Figure 2-1. CRG Block Diagram
System Reset
Bus Clock
Core Clock
Oscillator Clock
Real Time Interrupt
PLL Lock Interrupt
Self Clock Mode
Interrupt
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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