MC9S12XD256MAL Datasheet, PDF (968/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-70 lists the pin functions in relationship with the different operating modes. If two entries per pin
are displayed, a ‘mux’ indicates time-multiplexing between the two functions and an ‘or’ means that a
configuration bit exists which can be altered after reset to select the respective function (displayed in
italics). Refer to S12X_EBI section for details.
Table 23-70. Expanded Bus Pin Functions versus Operating Modes
Single-Chip Modes
Pin _{Normal Single- Special Single-}
Chip
Chip
PK7
GPIO
GPIO
PK[6:4]
GPIO
GPIO
PK[3:0]
GPIO
GPIO
PA[7:0]
GPIO
GPIO
PB[7:1]
GPIO
GPIO
PB0
GPIO
GPIO
PC[7:0]
GPIO
GPIO
PD[7:0]
PE7
PE6
PE5
PE4
PE3
GPIO
GPIO
or
ECLKX2
GPIO
GPIO
GPIO
or
ECLK
GPIO
GPIO
GPIO
or
ECLKX2
GPIO
GPIO
ECLK
or
GPIO
GPIO
PE2
GPIO
PJ5
GPIO
GPIO
GPIO
PJ4
GPIO
GPIO
Normal
Expanded
GPIO
or
EWAIT
ADDR[22:20]
or
GPIO
ADDR[19:16]
or
GPIO
ADDR[15:8]
or
GPIO
ADDR[7:1]
or
GPIO
UDS
or
GPIO
DATA[15:8]
or
GPIO
DATA[7:0]
GPIO
or
ECLKX2
GPIO
RE
ECLK
or
GPIO
LDS
or
GPIO
WE
GPIO
or
CS2
GPIO
or
CS0 ⁽¹⁾
Expanded Modes
Emulation
Single-Chip
GPIO
ADDR[22:20]
mux
ACC[2:0]
ADDR[19:16]
mux
IQSTAT[3:0]
ADDR[15:8]
mux
IVD[15:8]
ADDR[7:1]
mux
IVD[7:1]
ADDR0
mux
IVD0
DATA[15:8]
Emulation
Expanded
GPIO
or
EWAIT
ADDR[22:20]
mux
ACC[2:0]
ADDR[19:16]
mux
IQSTAT[3:0]
ADDR[15:8]
mux
IVD[15:8]
ADDR[7:1]
mux
IVD[7:1]
ADDR0
mux
IVD0
DATA[15:8]
DATA[7:0]
ECLKX2
DATA[7:0]
ECLKX2
TAGHI
TAGLO
ECLK
TAGHI
TAGLO
ECLK
LSTRB
LSTRB
R/W
GPIO
GPIO
R/W
GPIO
or
CS2
GPIO
or
CS0 ⁽¹⁾
Special
Test
GPIO
ADDR[22:20]
ADDR[19:16]
ADDR[15:8]
ADDR[7:1]
ADDR0
DATA[15:8]
or
GPIO
DATA[7:0]
GPIO
or
ECLKX2
GPIO
GPIO
ECLK
or
GPIO
LSTRB
R/W
GPIO
or
CS2
GPIO
or
CS0
MC9S12XDP512 Data Sheet, Rev. 2.21
970
Freescale Semiconductor