MC9S12XD256MAL Datasheet, PDF(961/1348 Page) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

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MC9S12XD256MAL Datasheet, PDF (961/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

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Table 23-67. Register Availability per Port1

Port

Data

Data

Direction

Input

Reduced

Drive

Pull

Enable

Polarity

Select

P

yes

yes

yes

yes

yes

yes

H

yes

yes

yes

yes

yes

yes

J

yes

yes

yes

yes

yes

yes

AD0

yes

yes

â

yes

yes

â

AD1

yes

yes

â

yes

yes

â

1. Each cell represents one register with individual conï¬guration bits

Wired-OR

Mode

â

â

â

â

â

Interrupt

Enable

yes

yes

yes

â

â

Interrupt

Flag

yes

yes

yes

â

â

23.0.6 Registers

23.0.6.1 Data Register

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output.

When reading this address, the buffered state of the pin is returned if the associated data direction

register bit is set to â0â.

If the data direction register bits are set to logic level â1â, the contents of the data register is

returned. This is independent of any other configuration (Figure 23-76).

23.0.6.2 Input Register

This is a read-only register and always returns the buffered state of the pin (Figure 23-76).

23.0.6.3 Data Direction Register

This register defines whether the pin is used as an input or an output.

If a peripheral module controls the pin the contents of the data direction register is ignored

(Figure 23-76).

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