MC9S12XD256MAL Datasheet, PDF (1269/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
fC
<
----------2-----^â‹---^ζ----^â‹---f--r--e----f---------
π
⋅
⎛
⎝
ζ
+
1 + ζ²_⎠⎞
⋅
1^--1-0^--
→
fC < ₄--f--r-_â‹--e-₁--f-₀- ;(ζ =
f_C < 100kHz
0.9 )
And finally the frequency relationship is defined as
n = ^{f--V--f-r--C-e---Of----} = 2 ⋅ (synr + 1)
= 20
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f_C = 20 kHz:
R = ^2-----â‹---^π---K--^â‹--_Φ-n-----^â‹---f--C---= ²-----_(â‹--₅-^π--₃---^â‹₉---_.2-₁--⁰-_H---^â‹--_z-²--₎-⁰---_⁄^k--_Ω-^H-----^z- = 4.7kΩ
The capacitance C_s can now be calculated as:
Cs = _π-----2_â‹---f--^â‹_C---^ζ---2_â‹---R--- = _{f-0-C--.--5--â‹}-1--R-6--;(ζ = 0.9)
= 5.5nF = ~ 4.7nF
The capacitance C_p should be chosen in the range of:
C-_{2---0-s- ≤ Cp ≤} C-_1---0-s-
C_P = 470pF
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock f_cmp, the
deviation from the reference clock f_ref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
0
1
2
3
N-1
N
t_min1
t_nom
t_max1
t_minN
t_maxN
Figure A-4. Jitter Definitions
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
1271