MC9S12XD256MAL Datasheet, PDF (986/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Register
Name
Bit 7
6
Non-PIM R
Address _W
Range
5
4
3
2
Non-PIM Address Range
PORTK R
0
PK7
PK5
PK4
PK3
PK2
W
DDRK R
0
DDRK7
DDRK5
DDRK4
DDRK3
DDRK2
W
Non-PIM R
Address _W
Range
Non-PIM Address Range
PTT R
PTT7
W
PTT6
PTT5
PTT4
PTT3
PTT2
PTIT R PTIT7
W
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
DDRT R
DDRT7
W
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
RDRT R
RDRT7
W
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
PERT R
PERT7
W
PERT6
PERT5
PERT4
PERT3
PERT2
PPST R
PPST7
W
PPST6
PPST5
PPST4
PPST3
PPST2
Reserved R
0
0
0
0
0
0
W
Reserved R
0
0
0
0
0
0
W
PTS R
PTS7
W
PTS6
PTS5
PTS4
PTS3
PTS2
PTIS R PTIS7
W
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
= Unimplemented or Reserved
Figure 24-2. PIM Register Summary (Sheet 3 of 7)
1
PK1
DDRK1
PTT1
PTIT1
DDRT1
RDRT1
PERT1
PPST1
0
0
PTS1
PTIS1
Bit 0
PK0
DDRK0
PTT0
PTIT0
DDRT0
RDRT0
PERT0
PPST0
0
0
PTS0
PTIS0
MC9S12XDP512 Data Sheet, Rev. 2.21
988
Freescale Semiconductor