MC9S12XD256MAL Datasheet, PDF (670/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU)
Address: 0x011F
7
R
1
W
6
SHU6
5
SHU5
4
SHU4
Reset
1
1
1
1
= Unimplemented or Reserved
3
SHU3
1
2
SHU2
1
1
SHU1
1
Figure 18-20. RAM Shared Region Upper Boundary Register (RAMSHU)
Read: Anytime
Write: Anytime when RWPE = 0
Table 18-18. RAMSHU Field Descriptions
0
SHU0
1
Field
6–0
SHU[6:0]
Description
RAM Shared Region Upper Boundary Bits 6–0 — These bits define the upper boundary of the shared
memory in multiples of 256 bytes. The block selected by this register is included in the region. See Figure 18-25
for details.
MC9S12XDP512 Data Sheet, Rev. 2.21
670
Freescale Semiconductor