MC9S12XD256MAL Datasheet, PDF (98/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.4 Functional Description
2.4.1 Functional Blocks
2.4.1.1 Phase Locked Loop (PLL)
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased
flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers
a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...
126,128 based on the SYNR register.
PLLCLK = 2 × OSCCLK × _[---^[_{R--S---E-Y---F--N--D--R---V---+--+---1--1--}^]--_]
CAUTION
Although it is possible to set the two dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1), Bus Clock = PLLCLK / 2
The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on
the difference between the output frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency f_SCM.
EXTAL
XTAL
REDUCED
CONSUMPTION ^OSCCLK
OSCILLATOR
REFDV <5:0>
REFERENCE
LOCK
FEEDBACK DETECTOR
LOCK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
UP
DOWN
V_DDPLL/V_SSPLL
CPUMP
VCO
CRYSTAL
MONITOR
supplied by:
V_DDPLL/V_SSPLL
V_DD/V_SS
LOOP
PROGRAMMABLE
DIVIDER
SYN <5:0>
V_DDPLL
LOOP
FILTER
XFC
PIN
PLLCLK
Figure 2-16. PLL Functional Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
98
Freescale Semiconductor