MC9S12XD256MAL Datasheet, PDF (668/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 18 Memory Mapping Control (S12XMMCV3)
Table 18-14. PPAGE Field Descriptions
Field
7–0
PIX[7:0]
Description
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
The fixed 16K page from 0x4000–0x7FFF (when ROMHM = 0) is the page number 0xFD.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
18.3.2.9 RAM Write Protection Control Register (RAMWPC)
Address: 0x011C
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-17. RAM Write Protection Control Register (RAMWPC)
Read: Anytime
Write: Anytime
Field
0
RWPE
1
AVIE
0
AVIF
Table 18-15. RAMWPC Field Descriptions
Description
RAM Write Protection Enable — This bit enables the RAM write protection mechanism. When the RWPE bit
is cleared, there is no write protection and any memory location is writable by the CPU module and the XGATE
module. When the RWPE bit is set the write protection mechanism is enabled and write access of the CPU or
to the XGATE RAM region. Write access performed by the XGATE module to outside of the XGATE RAM region
or the shared region is suppressed as well in this case.
0 RAM write protection check is disabled, region boundary registers can be written.
1 RAM write protection check is enabled, region boundary registers cannot be written.
CPU Access Violation Interrupt Enable — This bit enables the Access Violation Interrupt. If AVIE is set and
AVIF is set, an interrupt is generated.
0 CPU Access Violation Interrupt Disabled.
1 CPU Access Violation Interrupt Enabled.
CPU Access Violation Interrupt Flag — When set, this bit indicates that the CPU has tried to write a memory
location inside the XGATE RAM region. This flag can be reset by writing ’1’ to the AVIF bit location.
0 No access violation by the CPU was detected.
1 Access violation by the CPU was detected.
MC9S12XDP512 Data Sheet, Rev. 2.21
668
Freescale Semiconductor