MC9S12XD256MAL Datasheet, PDF (969/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 23-70. Expanded Bus Pin Functions versus Operating Modes (continued)
Single-Chip Modes
Expanded Modes
Pin _{Normal Single- Special Single-}
Chip
Chip
Normal
Expanded
Emulation
Single-Chip
Emulation
Expanded
Special
Test
PJ2
GPIO
PJ0
GPIO
GPIO
GPIO
GPIO
or
CS1
GPIO
or
CS3
GPIO
GPIO
GPIO
or
CS1
GPIO
or
CS3
GPIO
or
CS1
GPIO
or
CS3
1. Depending on ROMON bit. Refer to Device Guide, S12X_EBI section and S12X_MMC section for details.
23.0.10 Low-Power Options
23.0.10.1 Run Mode
No low-power options exist for this module in run mode.
23.0.10.2 Wait Mode
No low-power options exist for this module in wait mode.
23.0.10.3 Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H,
and J.
Initialization and Application Information
• It is not recommended to write PORTx and DDRx in a word access. When changing the
register pins from inputs to outputs, the data may have extra transitions during the write
access. Initialize the port data register before enabling the outputs.
• Power consumption will increase the more the voltages on general purpose input pins
deviate from the supply voltages towards mid-range because the digital input buffers
operate in the linear region.