MC9S12XD256MAL Datasheet, PDF (629/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU)
Address: 0x011D
7
R
1
W
Reset
1
6
XGU6
5
XGU5
4
XGU4
3
XGU3
2
XGU2
1
XGU1
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 17-18. RAM XGATE Upper Boundary Register (RAMXGU)
Read: Anytime
Write: Anytime when RWPE = 0
Table 17-15. RAMXGU Field Descriptions
0
XGU0
1
Field
6–0
XGU[6:0]
Description
XGATE Region Upper Boundary Bits 6-0 — These bits define the upper boundary of the RAM region allocated
to the XGATE module in multiples of 256 bytes. The 256 byte block selected by this register is included in the
region. See Figure 1-25 for details.
17.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL)
Address: 0x011E
7
R
1
W
6
SHL6
5
SHL5
4
SHL4
Reset
1
1
1
1
= Unimplemented or Reserved
3
SHL3
1
2
SHL2
1
1
SHL1
1
Figure 17-19. RAM Shared Region Lower Boundary Register (RAMSHL)
Read: Anytime
Write: Anytime when RWPE = 0
Table 17-16. RAMSHL Field Descriptions
0
SHL0
1
Field
6–0
SHL[6:0]
Description
RAM Shared Region Lower Boundary Bits 6–0 — These bits define the lower boundary of the shared memory
region in multiples of 256 bytes. The block selected by this register is included in the region. See Figure 1-25 for
details.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
629