MC9S12XD256MAL Datasheet, PDF (796/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 21 External Bus Interface (S12XEBIV2)
21.4.2.2.3 Read-Write-Read Access Timing
Table 21-15. Interleaved Read-Write-Read Accesses (1 Cycle)
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0] ...
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0] ...
DATA[15:0] (internal read) ...
DATA[15:0] (external read) ...
R/W
...
Access #0
1
high
low
acc 0
addr 0 iqstat -1
?
?
z
?
z
1
1
Access #1
Access #2
2
3
...
high
low
high
low ...
acc 1
acc 2 ...
addr 1
iqstat 0
addr 2
iqstat 1 ...
ivd 0
x
...
z
(write) data 1
z
...
data 0
(write) data 1
z
...
0
0
1
1
...
21.4.2.3 Internal Visibility Data
Depending on the access size and alignment, either a word of read data is made visible on the address lines
or only the related data byte will be presented in the ECLK low phase. For details refer to Table 21-16.
Table 21-16. IVD Read Data Output
Access
Word read of data at an even and even+1 address
Word read of data at an odd and odd+1 internal RAM address (misaligned)
Byte read of data at an even address
Byte read of data at an odd address
IVD[15:8]
ivd(even)
ivd(odd+1)
ivd(even)
addr[15:8] (rep.)
IVD[7:0]
ivd(even+1)
ivd(odd)
addr[7:0] (rep.)
ivd(odd)
21.4.3 Accesses to Port Replacement Registers
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
21.4.4 Stretched External Bus Accesses
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states).
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
MC9S12XDP512 Data Sheet, Rev. 2.21
798
Freescale Semiconductor