MC9S12XD256MAL Datasheet, PDF (1251/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
A.2 ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
A.2.1 ATD Operating Characteristics
The Table A-12 and Table A-13 show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-12. ATD 5-V Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 4.5 V < V_DDA < 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 D Reference potential
Low
High
2 C Differential reference voltage¹
V_RL
V_SSA
—
V_DDA/2
V
V_RH
V_DDA/2
—
V_DDA
V
V_RH-V_RL
4.50
5.00
5.5
V
3 D ATD clock frequency
f_ATDCLK
0.5
2.0
MHz
4 D ATD 10-bit conversion period
Clock cycles²
Conv, time at 2.0 MHz ATD clock f_ATDCLK
N_CONV10
14
—
28
Cycles
T_CONV10
7
—
14
µs
5 D ATD 8-Bit conversion period
Clock cycles²
Conv, time at 2.0 MHz ATD clock f_ATDCLK
N_CONV8
12
—
26
Cycles
T_CONV8
6
—
13
µs
6 D Recovery time (V_DDA = 5.0 Volts)
t_REC
—
—
20
µs
7 P Reference supply current 2 ATD blocks on
I_REF
—
—
0.750
mA
8 P Reference supply current 1 ATD block on
I_REF
—
—
0.375
mA
1 _{Full accuracy is not guaranteed when differential voltage is less than 4.50 V}
2 _{The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample}
period of 16 ATD clocks.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
1253