MC9S12XD256MAL Datasheet, PDF (351/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Bus Clock
P0
P1
P2
P3
P4
P5
P6
P7
÷ 1, 2, ..., 128
Timer Prescaler
16-Bit Free-Running
16 BITMMaiAnINTimTIeMrER
Bus Clock
÷ 1, 4, 8, 16
Modulus Prescaler
Pin Logic
Delay
Counter
EDG0
Comparator
TC0 Capture/Compare Reg.
16-Bit Load Register
16-Bit Modulus
Down Counter
0 ^RESET
PAC0
Pin Logic
Delay
Counter
EDG1
TC0H Hold Reg.
Comparator
TC1 Capture/Compare Reg.
PA0H Hold Reg.
0 ^RESET
PAC1
Pin Logic
Delay
Counter
EDG2
TC1H Hold Reg.
Comparator
TC2 Capture/Compare Reg.
PA1H Hold Reg.
0 ^RESET
PAC2
Pin Logic
Delay
Counter
EDG3
TC2H Hold Reg.
Comparator
TC3 Capture/Compare Reg.
PA2H Hold Reg.
0 ^RESET
PAC3
TC3H Hold Reg.
PA3H Hold Reg.
Pin Logic _EDG4
EDG0
SH04
MUX
Pin Logic _EDG5
EDG1
SH15
MUX
Comparator
TC4 Capture/Compare Reg.
ICLAT, LATQ, BUFEN
(Force Latch)
Comparator
TC5 Capture/Compare Reg.
Write 0x0000
to Modulus Counter
Pin Logic _EDG6
EDG2
SH26
MUX
Comparator
TC6 Capture/Compare Reg.
LATQ
(MDC Latch Enable)
Pin Logic _EDG7
EDG3
SH37
MUX
Comparator
TC7 Capture/Compare Reg.
Figure 7-65. Detailed Timer Block Diagram in Latch Mode when PRNT = 0
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
351