MC9S12XD256MAL Datasheet, PDF (904/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-1. Pin Functions and Priorities (Sheet 3 of 7)
Port
K
T
S
Pin Name
Pin Function
and Priority
ROMCTL¹
PK[7]
EWAIT
PK[6:4]
PK[3:0]
PT[7:0]
GPIO
ADDR[22:20]
mux
ACC[2:0]²
GPIO
ADDR[19:16]
mux
IQSTAT[3:0]²
GPIO
IOC[7:0]
GPIO
SS0
PS7
GPIO
SCK0
PS6
GPIO
MOSI0
PS5
GPIO
MISO0
PS4
GPIO
TXD1
PS3
GPIO
RXD1
PS2
GPIO
TXD0
PS1
GPIO
RXD0
PS0
GPIO
I/O
Description
I ROMON bit control input during RESET
I
External Wait signal
Configurable for reduced input threshold
I/O General-purpose I/O
O
Extended external bus address output
(multiplexed with access master output)
I/O General-purpose I/O
O
Extended external bus address output
(multiplexed with instruction pipe status bits)
I/O General-purpose I/O
I/O Enhanced Capture Timer Channels 7–0 input/output
I/O General-purpose I/O
I/O
Serial Peripheral Interface 0 slave select output in master
mode, input in slave mode or master mode.
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 serial clock pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master out/slave in pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master in/slave out pin
I/O General-purpose I/O
O Serial Communication Interface 1 transmit pin
I/O General-purpose I/O
I Serial Communication Interface 1 receive pin
I/O General-purpose I/O
O Serial Communication Interface 0 transmit pin
I/O General-purpose I/O
I Serial Communication Interface 0 receive pin
I/O General-purpose I/O
Pin Function
after Reset
Mode
dependent³
GPIO
GPIO
MC9S12XDP512 Data Sheet, Rev. 2.21
906
Freescale Semiconductor