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MC9S12XD256MAL Datasheet, PDF (442/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Field
7:0
AC[7:0]
Table 10-20. CANIDAR0âCANIDAR3 Register Field Descriptions
Description
Acceptance Code Bits â AC[7:0] comprise a user-deï¬ned sequence of bits with which the corresponding bits
of the related identiï¬er register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identiï¬er mask register.
Module Base + 0x0018 (CANIDAR4)
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 10-21. MSCAN Identiï¬er Acceptance Registers (Second Bank) â CANIDAR4âCANIDAR7
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S12XDP512 Data Sheet, Rev. 2.21
442
Freescale Semiconductor
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