MC9S12XD256MAL Datasheet, PDF (693/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE
module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG
module armed, the DBG remains armed.
The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if
the MCU is secure.
Table 19-1. Mode Dependent Restriction Summary
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
MCU
Secure
1
0
0
0
0
Comparator Matches
Enabled
Breakpoints
Possible
Tagging
Possible
Yes
Yes
Yes
Yes
Only SWI
Yes
Yes
XGATE only
Active BDM not possible when not enabled
Yes
Yes
XGATE only
XGATE only
Tracing
Possible
No
Yes
Yes
XGATE only
19.1.4 Block Diagram
Figure 19-1 shows a block diagram of the debug module.
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
TAGS
BREAKPOINT REQUESTS
CPU & XGATE
CPU BUS
XGATE BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MATCH0
MATCH1
MATCH2
MATCH3
TAG & TRIGGER
TRIGGER
CONTROL
LOGIC
STATE
STATE
SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
TRACE
BUFFER
Figure 19-1. Debug Block Diagram
19.2 External Signal Description
The DBG sub-module features two external tag input signals (see Table 19-2). See Device User Guide
(DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging
in emulation modes only
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
695