MC9S12XD256MAL Datasheet, PDF (573/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 15 Background Debug Module (S12XBDMV2)
15.3.2 Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 15-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global Register
Address Name
Bit 7
6
5
0x7FFF00 Reserved R X
X
X
W
0x7FFF01 BDMSTS R
BDMACT
0
ENBDM
W
0x7FFF02 Reserved R X
X
X
W
0x7FFF03 Reserved R X
X
X
W
0x7FFF04 Reserved R X
X
X
W
0x7FFF05 Reserved R X
X
X
W
0x7FFF06 BDMCCRL R
CCR7
W
CCR6
CCR5
0x7FFF07 BDMCCRH R
0
0
0
W
0x7FFF08 BDMGPR R
BGAE
W
BGP6
BGP5
0x7FFF09 Reserved R
0
0
0
W
0x7FFF0A Reserved R
0
0
0
W
0x7FFF0B Reserved R
0
0
0
W
4
3
2
1
Bit 0
X
X
X
0
0
SDV
TRACE
UNSEC
0
CLKSW
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CCR4
CCR3
CCR2
CCR1
CCR0
0
0
CCR10 CCR9
CCR8
BGP4
BGP3
BGP2
BGP1
BGP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented, Reserved
X
= Indeterminate
0
Figure 15-2. BDM Register Summary
= Implemented (do not alter)
= Always read zero
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
573