MC9S12XD256MAL Datasheet, PDF (991/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Field
7–0
PA[7:0]
Table 24-4. PORTA Field Descriptions
Description
Port A — Port A pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
24.0.5.2 Port B Data Register (PORTB)
7
R
PB7
W
6
PB6
5
PB5
4
PB4
3
PB3
2
PB2
1
PB1
0
PB0
Reset
0
0
0
0
0
0
0
0
Figure 24-4. Port B Data Register (PORTB)
Read: Anytime.
Write: Anytime.
Table 24-5. PORTB Field Descriptions
Field
7–0
PB[7:0]
Description
Port B — Port B pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O
pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state
is read.
24.0.5.3 Port A Data Direction Register (DDRA)
R
W
Reset
7
DDRA7
0
Read: Anytime.
Write: Anytime.
6
DDRA6
5
DDRA5
4
DDRA4
3
DDRA3
2
DDRA2
0
0
0
0
0
Figure 24-5. Port A Data Direction Register (DDRA)
Table 24-6. DDRA Field Descriptions
1
DDRA1
0
0
DDRA0
0
Field
Description
7–0
DDRA[7:0]
Data Direction Port A — This register controls the data direction for port A. DDRA determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTA after changing the DDRA register.