MC9S12XD256MAL Datasheet, PDF (249/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

CMP
Compare
Chapter 6 XGATE (S12XGATEV2)
CMP
Operation
RS2 – RS1 ⇒ NONE (translates to SUB R0, RS1, RS2)
RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8])
Subtracts two 16 bit values and discards the result.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]
RD[15] & IMM16[15] & result[15] | RD[15] & IMM16[15] & result[15]
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]
RD[15] & IMM16[15] | RD[15] & result[15] | IMM16[15] & result[15]
Code and CPU Cycles
Source Form
CMP RS1, RS2
CMP RS, #IMM16
Address
Mode
TRI
IMM8
IMM8
Machine Code
00011000
1 1 0 1 0 RS
1 1 0 1 1 RS
RS1
RS2 0 0
IMM16[7:0]
IMM16[15:8]
Cycles
P
P
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
249