MC9S12XD256MAL Datasheet, PDF (919/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Field
7–0
PA[7:0]
Table 23-4. PORTA Field Descriptions
Description
Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively inexpanded
modesWhen this port is not used for external addresses, these pins can be used as general purpose I/O. If the
data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,
otherwise the buffered pin input state is read.
23.0.5.2 Port B Data Register (PORTB)
7
R
PB7
W
6
PB6
5
PB5
4
PB4
3
PB3
2
PB2
1
PB1
0
PB0
Reset
0
0
0
0
0
0
0
0
Figure 23-4. Port B Data Register (PORTB)
Read: Anytime.
Write: Anytime.
Table 23-5. PORTB Field Descriptions
Field
7–0
PB[7:0]
Description
Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded
modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data
Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be
used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
23.0.5.3 Port A Data Direction Register (DDRA)
R
W
Reset
7
DDRA7
0
6
DDRA6
5
DDRA5
4
DDRA4
3
DDRA3
2
DDRA2
0
0
0
0
0
Figure 23-5. Port A Data Direction Register (DDRA)
1
DDRA1
0
0
DDRA0
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.