MC9S12XD256MAL Datasheet, PDF (911/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 23-2. PIM Memory Map (Sheet 3 of 3)
Address
Use
Access
0x026B
0x026C
0x026D
0x026E
0x026F
Port J Reduced Drive Register (RDRJ)
Port J Pull Device Enable Register (PERJ)
Port J Polarity Select Register (PPSJ)
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
Read / Write¹
Read / Write¹
Read / Write¹
Read / Write¹
Read / Write¹
0x0270 PIM Reserved
—
0x0271 Port AD0 Data Register 1 (PT1AD0)
Read / Write
0x0272 PIM Reserved
—
0x0273 Port AD0 Data Direction Register 1 (DDR1AD0)
Read / Write
0x0274 PIM Reserved
—
0x0275 Port AD0 Reduced Drive Register 1 (RDR1AD0)
Read / Write
0x0276 PIM Reserved
—
0x0277 Port AD0 Pull Up Enable Register 1 (PER1AD0)
Read / Write
0x0278 Port AD1 Data Register 0 (PT0AD1)
Read / Write
0x0279 Port AD1 Data Register 1 (PT1AD1)
Read / Write
0x027A Port AD1 Data Direction Register 0 (DDR0AD1)
Read / Write
0x027B Port AD1 Data Direction Register 1 (DDR1AD1)
Read / Write
0x027C Port AD1 Reduced Drive Register 0 (RDR0AD1)
Read / Write
0x027D Port AD1 Reduced Drive Register 1 (RDR1AD1)
Read / Write
0x027E Port AD1 Pull Up Enable Register 0 (PER0AD1)
Read / Write
0x027F Port AD1 Pull Up Enable Register 1 (PER1AD1)
Read / Write
1. Write access not applicable for one or more register bits. Refer to Section 23.0.5, “Regis-
ter Descriptions”.
23.0.5 Register Descriptions
Table 23-3 summarizes the effect on the various configuration bits, data direction (DDR), output
level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the
ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.