MC9S12XD256MAL Datasheet, PDF (778/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
Field
7
CSD
6
CVA
4
CDV
Table 20-41. CINF Field Descriptions
Description
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source Address
1 Destination Address
Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. This is only used
in Normal and Loop1 mode tracing.
0 Source Address
1 Destination Address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the S12XCPU trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
CXINF Information Byte
Bit 7
CFREE
Bit 6
CSZ
Bit 5
CRW
Bit 4
COCF
Bit 3
XACK
Bit 2
XSZ
Figure 20-26. Information Byte CXINF
Bit 1
XRW
Bit 0
XOCF
This describes the format of the information byte used only when tracing from S12XCPU or XGATE in
Detail Mode. When tracing from the S12XCPU in Detail Mode, information is stored to the trace buffer
on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot
of the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made
by the S12XCPU, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free
cycle (no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail
Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The
S12XCPU entry stored on the same line is a snapshot of the S12XCPU program counter. In this case the
XSZ and XRW bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF
bits indicate if the simultaneous S12XCPU cycle is a free cycle or opcode fetch cycle.
Table 20-42. CXINF Field Descriptions
Field
7
CFREE
6
CSZ
Description
S12XCPU Free Cycle Indicator — This bit indicates if the stored S12XCPU address corresponds to a free cycle.
This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle
Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains
valid information when tracing S12XCPU activity in Detail Mode.
0 Word Access
1 Byte Access
MC9S12XDP512 Data Sheet, Rev. 2.21
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