MC9S12XD256MAL Datasheet, PDF (944/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-42. PPSP Field Descriptions
Field
Description
7–0
PPSP[7:0]
Polarity Select Port P
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
23.0.5.44 Port P Interrupt Enable Register (PIEP)
R
W
Reset
7
PIEP7
0
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
0
0
0
0
0
Figure 23-46. Port P Interrupt Enable Register (PIEP)
1
PIEP1
0
0
PIEP0
0
Read: Anytime.
Write: Anytime.
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port P.
Table 23-43. PIEP Field Descriptions
Field
Description
7–0
PIEP[7:0]
Interrupt Enable Port P
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
23.0.5.45 Port P Interrupt Flag Register (PIFP)
R
W
Reset
7
PIFP7
0
Read: Anytime.
Write: Anytime.
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
0
0
0
0
0
Figure 23-47. Port P Interrupt Flag Register (PIFP)
1
PIFP1
0
0
PIFP0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
946
Freescale Semiconductor