MC9S12XD256MAL Datasheet, PDF (1007/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Table 24-29. DDRM Field Descriptions
Field
Description
7–0
DDRM[7:0]
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTM or PTIM registers, when changing the DDRM register.
24.0.5.29 Port M Reduced Drive Register (RDRM)
R
W
Reset
7
RDRM7
0
6
RDRM6
5
RDRM5
4
RDRM4
3
RDRM3
2
RDRM2
0
0
0
0
0
Figure 24-31. Port M Reduced Drive Register (RDRM)
1
RDRM1
0
0
RDRM0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port M output pin as either full or reduced. If the
port is used as input this bit is ignored.
Table 24-30. RDRM Field Descriptions
Field
Description
7–0
Reduced Drive Port M
RDRM[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
24.0.5.30 Port M Pull Device Enable Register (PERM)
R
W
Reset
7
PERM7
0
Read: Anytime.
Write: Anytime.
6
PERM6
5
PERM5
4
PERM4
3
PERM3
2
PERM2
0
0
0
0
0
Figure 24-32. Port M Pull Device Enable Register (PERM)
1
PERM1
0
0
PERM0
0