MC9S12XD256MAL Datasheet, PDF (857/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.43 Port P Polarity Select Register (PPSP)
R
W
Reset
7
PPSP7
0
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
0
0
0
0
0
Figure 22-45. Port P Polarity Select Register (PPSP)
1
PPSP1
0
0
PPSP0
0
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
Table 22-42. PPSP Field Descriptions
Field
Description
7–0
PPSP[7:0]
Polarity Select Port P
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
22.3.2.44 Port P Interrupt Enable Register (PIEP)
R
W
Reset
7
PIEP7
0
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
0
0
0
0
0
Figure 22-46. Port P Interrupt Enable Register (PIEP)
1
PIEP1
0
0
PIEP0
0
Read: Anytime.
Write: Anytime.
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port P.
Table 22-43. PIEP Field Descriptions
Field
Description
7–0
PIEP[7:0]
Interrupt Enable Port P
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
859