MC9S12XD256MAL Datasheet, PDF (815/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3 Memory Map and Register Definition
This section provides a detailed description of all PIM registers.
22.3.1 Module Memory Map
Table 22-2 shows the register map of the port integration module.
Table 22-2. PIM Memory Map (Sheet 1 of 3)
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
:
0x000B
0x000C
0x000D
0x000E
:
0x001B
0x001C
0x001D
0x001E
0x001F
0x0020
:
0x0031
0x0032
0x0033
0x0034
:
0x023F
0x0240
Use
Port A Data Register (PORTA)
Port B Data Register (PORTB)
Port A Data Direction Register (DDRA)
Port B Data Direction Register (DDRB)
Port C Data Register (PORTC)
Port D Data Register (PORTD)
Port C Data Direction Register (DDRC)
Port D Data Direction Register (DDRD)
Port E Data Register (PORTE)
Port E Data Direction Register (DDRE)
Non-PIM Address Range
Pull-up Up Control Register (PUCR)
Reduced Drive Register (RDRIV)
Non-PIM Address Range
ECLK Control Register (ECLKCTL)
PIM Reserved
IRQ Control Register (IRQCR)
PIM Reserved
Non-PIM Address Range
Port K Data Register (PORTK)
Port K Data Direction Register (DDRK)
Non-PIM Address Range
Port T Data Register (PTT)
Access
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write¹
Read / Write¹
—
Read / Write¹
Read / Write¹
—
Read / Write¹
—
Read / Write¹
—
—
Read / Write
Read / Write
—
Read / Write
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
817