MC9S12XD256MAL Datasheet, PDF (313/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Table 7-1. ECT Memory Map (continued)
Address
Offset
Register
Access
0x001E
0x001F
Timer Input Capture/Output Compare Register 7 High (TC7)
Timer Input Capture/Output Compare Register 7 Low (TC7)
R/W³
R/W³
0x0020 16-Bit Pulse Accumulator A Control Register (PACTL)
R/W
0x0021 Pulse Accumulator A Flag Register (PAFLG)
R/W
0x0022 Pulse Accumulator Count Register 3 (PACN3)
R/W
0x0023 Pulse Accumulator Count Register 2 (PACN2)
R/W
0x0024 Pulse Accumulator Count Register 1 (PACN1)
R/W
0x0025 Pulse Accumulator Count Register 0 (PACN0)
R/W
0x0026 16-Bit Modulus Down Counter Register (MCCTL)
R/W
0x0027 16-Bit Modulus Down Counter Flag Register (MCFLG)
R/W
0x0028 Input Control Pulse Accumulator Register (ICPAR)
R/W
0x0029 Delay Counter Control Register (DLYCT)
R/W
0x002A
0x002B
Input Control Overwrite Register (ICOVW)
Input Control System Control Register (ICSYS)
R/W
R/W⁴
0x002C
0x002D
Reserved
Timer Test Register (TIMTST)
--
R/W²
0x002E Precision Timer Prescaler Select Register (PTPSR)
R/W
0x002F Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
R/W
0x0030 16-Bit Pulse Accumulator B Control Register (PBCTL)
R/W
0x0031
0x0032
0x0033
0x0034
0x0035
16-Bit Pulse Accumulator B Flag Register (PBFLG)
8-Bit Pulse Accumulator Holding Register 3 (PA3H)
8-Bit Pulse Accumulator Holding Register 2 (PA2H)
8-Bit Pulse Accumulator Holding Register 1 (PA1H)
8-Bit Pulse Accumulator Holding Register 0 (PA0H)
R/W
R/W⁵
R/W⁵
R/W⁵
R/W⁵
0x0036 Modulus Down-Counter Count Register High (MCCNT)
R/W
0x0037
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
0x003E
0x003F
Modulus Down-Counter Count Register Low (MCCNT)
Timer Input Capture Holding Register 0 High (TC0H)
Timer Input Capture Holding Register 0 Low (TC0H)
Timer Input Capture Holding Register 1 High(TC1H)
Timer Input Capture Holding Register 1 Low (TC1H)
Timer Input Capture Holding Register 2 High (TC2H)
Timer Input Capture Holding Register 2 Low (TC2H)
Timer Input Capture Holding Register 3 High (TC3H)
Timer Input Capture Holding Register 3 Low (TC3H)
R/W
R/W⁵
R/W⁵
R/W⁵
R/W⁵
R/W⁵
R/W⁵
R/W⁵
R/W⁵
1 _{Always read 0x0000.}
2 _{Only writable in special modes (test_mode = 1).}
3 _{Writes to these registers have no meaning or effect during input capture.}
4 _{May be written once when not in test00mode but writes are always permitted when test00mode is enabled.}
5 _{Writes have no effect.}
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
313