MC9S12XD256MAL Datasheet, PDF (186/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
6.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the XGATE module.
The memory map for the XGATE module is given below in Figure 6-2.The address listed for each register
is the sum of a base address and an address offset. The base address is defined at the SoC level and the
address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved
registers have no effect.
6.3.1 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
15 14 13 12 11 10 9 8 7 6 5 4 3
XGMCTL R 0 0 0 0 0 0 0 0
W ^XGEM
XG
FRZM
XG
DBGM
XGSSM
XG
FACTM
XG
SWEIFM
XGIEM
XGE
XGFRZ XGDBG XGSS
XG
FACT
210
0
XG
SWEIF
XGIE
XGMCHID R
W
0
XGCHID[6:0]
Reserved R
W
Reserved R
W
Reserved R
W
XGVBR R
0
XGVBR[15:1]
W
= Unimplemented or Reserved
Figure 6-2. XGATE Register Summary (Sheet 1 of 3)
MC9S12XDP512 Data Sheet, Rev. 2.21
186
Freescale Semiconductor