MC9S12XD256MAL Datasheet, PDF (746/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
Pin Name
TAGHI
(See DUG)
TAGLO
(See DUG)
TAGLO
(See DUG)
Table 20-2. External System Pins Associated With S12XDBG
Pin Functions
TAGHI
TAGLO
Unconditional
Tagging Enable
Description
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
20.3 Memory Map and Registers
20.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 20-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address
0x0020
Name
R
DBGC1
W
0x0021
R
DBGSR
W
R
0x0022 DBGTCR
W
0x0023
R
DBGC2
W
0x0024
R
DBGTBH
W
0x0025
R
DBGTBL
W
R
0x0026 DBGCNT
W
0x0027
0x0027
R
DBGSCRX
W
R
DBGMFR
W
0x0028¹
0x0028²
DBGXCTL R
(COMPA/C) W
DBGXCTL R
(COMPB/D) W
R
0x0029 DBGXAH
W
Bit 7
ARM
TBF
6
0
TRIG
EXTF
TSOURCE
0
0
Bit 15
Bit 14
Bit 7
Bit 6
0
0
0
0
0
0
NDB
SZE
SZ
0
Bit 22
5
XGSBPE
0
4
BDM
0
TRANGE
0
0
Bit 13
Bit 12
Bit 5
Bit 4
0
0
0
0
TAG
BRK
TAG
BRK
21
20
3
2
DBGBRK
0
SSF2
TRCMOD
CDCM
Bit 11
Bit 10
Bit 3
Bit 2
CNT
SC3
MC3
SC2
MC2
RW
RWE
RW
RWE
19
18
1
Bit 0
COMRV
SSF1
SSF0
TALIGN
ABCM
Bit 9
Bit 8
Bit 1
Bit 0
SC1
MC1
SC0
MC0
SRC
SRC
COMPE
COMPE
17
Bit 16
Figure 20-2. Quick Reference to S12XDBG Registers
MC9S12XDP512 Data Sheet, Rev. 2.21
748
Freescale Semiconductor