MC9S12XD256MAL Datasheet, PDF (837/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Table 22-20. DDRK Field Descriptions
Field
Description
7–0
DDRK[7:0]
Data Direction Port K
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTK after changing the DDRK register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
839