MC9S12XD256MAL Datasheet, PDF (217/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

ADD
Add without Carry
Chapter 6 XGATE (S12XGATEV2)
ADD
Operation
RS1 + RS2 ⇒ RD
RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8])
Performs a 16 bit addition and stores the result in the destination register RD.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]_new | RS1[15] & RS2[15] & RD[15]_new
Refer to ADDH instruction for #IMM16 operations.
C: Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]_new | RS2[15] & RD[15]_new
Refer to ADDH instruction for #IMM16 operations.
Code and CPU Cycles
Source Form
ADD RD, RS1, RS2
ADD RD, #IMM16
Address
Mode
TRI
IMM8
IMM8
00011
11100
11101
Machine Code
Cycles
RD
RS1
RS2 1 0
P
RD
IMM16[7:0]
P
RD
IMM16[15:8]
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
217