MC9S12XD256MAL Datasheet, PDF (871/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.61 Port J Interrupt Flag Register (PIFJ)
R
W
Reset
7
PIFJ7
0
6
5
4
3
2
0
PIFJ6
PIFJ5
PIFJ4
PIFJ2
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-63. Port J Interrupt Flag Register (PIFJ)
1
PIFJ1
0
0
PIFJ0
0
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
Table 22-57. PIEJ Field Descriptions
Field
7–0
PIFJ[7:4]
PIFJ[2:0]
Description
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
22.3.2.62 Port AD0 Data Register 1 (PT1AD0)
7
R
PT1AD07
W
6
PT1AD06
5
PT1AD05
4
PT1AD04
3
PT1AD03
2
PT1AD02
1
PT1AD01
0
PT1AD00
Reset
0
0
0
0
0
0
0
0
Figure 22-64. Port AD0 Data Register 1 (PT1AD0)
Read: Anytime.
Write: Anytime.
This register is associated with AD0 pins PAD[7:0]. These pins can also be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
873