MC9S12XD256MAL Datasheet, PDF (1011/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

24.0.5.36 Port P Data Direction Register (DDRP)
R
W
Reset
7
DDRP7
0
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
0
0
0
0
0
Figure 24-38. Port P Data Direction Register (DDRP)
1
DDRP1
0
0
DDRP0
0
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–
0 channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM
section for details.
If SPI is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are
disabled.
Table 24-35. DDRP Field Descriptions
Field
Description
7–0
DDRP[7:0]
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTP or PTIP registers, when changing the DDRP register.
24.0.5.37 Port P Reduced Drive Register (RDRP)
R
W
Reset
7
RDRP7
0
6
RDRP6
5
RDRP5
4
RDRP4
3
RDRP3
2
RDRP2
0
0
0
0
0
Figure 24-39. Port P Reduced Drive Register (RDRP)
1
RDRP1
0
0
RDRP0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port P output pin as either full or reduced. If the
port is used as input this bit is ignored.